1. Field of the Invention
The present invention generally relates to semiconductor devices and integrated circuits formed on substrates containing an insulator layer such as silicon-on-insulator chip or wafer and, more particularly, to the control of floating body effects in transistors formed on such substrates.
2. Description of the Prior Art
Demands for increased performance, functionality and manufacturing economy for integrated circuits have resulted in extreme integration density to reduce signal propagation time and increase noise immunity while increasing the number of circuits and devices that can be formed on a chip or wafer by a single sequence of processes. Scaling of devices to small sizes has also restricted operating margins and required increased uniformity of electrical characteristics of semiconductor devices on a chip.
To satisfy this latter criterion, silicon-on-insulator (SOI) wafers have been used to exploit the improved quality of monocrystalline silicon provided thereby in an active layer formed on an insulator over a bulk silicon xe2x80x9chandlingxe2x80x9d substrate. Similar attributes can be developed in similar structures of other semiconductor materials and alloys thereof. The improved quality of the semiconductor material of the active layer allows transistors and other devices to be scaled to extremely small sizes with good uniformity of electrical properties.
Unfortunately, the existence of the insulator layer which supports the development of the improved quality of semiconductor material also presents a problem known in the art as floating body effect in transistor structures. The floating body effect is specific to transistors formed on substrates having an insulator layer. The neutral floating body is electrically isolated by source/drain and halo extension regions that form oppositely poled diode junctions at the ends of the transistor conduction channel and floating body while the gate electrode is insulated from the conduction channel through a dielectric. The insulator layer in the substrate completes insulation of the conduction channel and thus prevents discharge of any charge that may develop in the floating body. Charge injection into the neutral body when the transistor is not conducting develops voltages in the conduction channel in accordance with the source and drain diode characteristics.
The voltage developed due to charge collection in the transistor conduction channel has the effect of altering the switching threshold of the transistor. This effect, in turn, alters the signal timing and signal propagation speed since any transistor will have a finite slew rate and the rise and fall time of signals is not instantaneous even when gate capacitance is very small. Therefore, the diode characteristics of the source and drain must be tailored to limit charge build-up in the floating body.
To do so, the diode junctions must be made somewhat leaky to allow the floating body of the transistor to be discharged to an acceptable degree. Unfortunately, since field effect transistors are generally formed symmetrically with identical source and drain impurity structures, development of such a characteristic reduces the ratio of resistance of the xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d states of the transistor, often referred to as the on/off ratio. A large on/off ratio is desirable to support maximum circuit fanout (the number of transistor gates a transistor can drive with acceptable switching speed) and to provide maximum signal voltage swing close to the power supply voltage. Therefore, there is a trade-off between limitation of floating body effects and maintaining a suitable on/off ratio.
While most known designs for field effect transistors are symmetrical, asymmetrical FETs have been proposed and investigated by simulation, but possibly not realized, for reduction of short channel and hot carrier effects and/or suppression of parasitic bipolar transistor effects (but not reduction of floating body effects), as reported, for example, in xe2x80x9cAn 0.1-xcexcm Asymmetric Halo by Large-Angle-Tilt Implant (AHLATI) MOSFET for High Performance and Reliabilityxe2x80x9d by Shin et al., IEEE Transactions on Electron Devices, Vol. 46, No. 4, April 1999, and xe2x80x9cA High Performance 0.1 xcexcm MOSFET with Asymmetric Channel Profilexe2x80x9d by A. Hiroki et al. IEEE, 1995.
These approaches use angled implants which are asymmetrically placed due to shadowing by a (possibly dummy) gate structure and are largely characterized by substantial process complexity and diffusion of impurities over substantial distances which prevents the formation of sharp impurity concentration gradients and results in low precision of impurity structure placement. The proposed processes also do not provide for differences in impurity concentration between the source and drain but only differences in location. In summary, while some asymmetry is provided, the flexibility of design parameters in accordance with the proposed processes is very limited and, while source and drain characteristics may be made to differ somewhat, the diode characteristics cannot be accurately tailored or independently fabricated.
The approach to reduction of floating body effects at the present state of the art is to form a connection from the floating body/conduction channel to the source electrode through the impurity well. This approach is only a partial solution since the well can be highly resistive and the connection can be ineffective. Further, the connection requires additional chip space and therefore precludes achievement of the potential integration density that would otherwise be possible.
It is also known in fabrication of integrated circuits at very small feature size regimes to form conductive structures such as interconnects by a Damascene process; yielding structures of superior stability, accuracy and other mechanical properties. A Damascene process involves formation of a recess at a surface, depositing metal in the recess and planarizing the deposited metal to the surface. This produces a conductive structure of very precise dimensions and which is laterally supported at all times and is therefore particularly resistant to metal migration and damage in interconnect structures.
More recently, in an effort to achieve higher conductivity of gate structures, metal gates have been developed and a Damascene process has been proposed for fabrication of the same, as reported in, for example, xe2x80x9cDamascene-Gate Thin Film Transistors with Ultra-Thin Gate Dielectricsxe2x80x9d by E. Ma et al., IEEE 1998. However, process complexity is substantial and, moreover, metal gate transistors have been found to present difficulties in obtaining a desired work function difference between NMOS and PMOS devices.
A Damascene gate can also be used to allow formation of the gate dielectric and gate electrode subsequent to source and drain implantation with a dummy gate as reported in xe2x80x9cPlasma Damage Free Gate Process Using Chemical Mechanical Polishing for 0.1 xcexcm MOSFETsxe2x80x9d by T. Saito et al., Japanese Journal of Applied Physics; April, 1999. However, since a dummy gate structure is used for source/drain implantation, substantial process complexity is required to obtain correct gate structure registration and the Damascene process must be performed after the source/drain implantation processes are complete. Moreover, use of a dummy gate structure cannot serve to increase location accuracy or concentration gradient of impurity structures such as halo and extension implants as discussed above.
It is therefore an object of the present invention to provide a method of fabricating a transistor on a SOI substrate which can be made substantially free of floating body effects by allowing tailoring of diode characteristics of the source and/or drain of the transistor.
It is another object of the invention to provide a simplified process for fabrication of an asymmetric field effect transistor which provides improved accuracy of location and concentration gradient of impurity structures for improved performance.
In order to accomplish these and other objects of the invention, a method of forming an asymmetric field effect transistor to control floating body effect and a transistor having reduced or eliminated floating body effects formed by such a process is provided wherein the method or process includes steps of defining a gate location with a trench in a dielectric layer on a semiconductor layer, supplying impurities to the semiconductor layer at edges of the trench and adjacent source and drain regions, and forming a gate structure on the semiconductor layer in the trench. The impurities are supplied by angled implantation and/or diffusion from a doped solid body formed in the trench to accurately locate desired impurities such that diffusion is not required to drive the impurities to a desired location; thus supporting steep impurity concentration gradients and high performance.